The vertical trench-gated power MOSFET has rapidly displaced all other forms of low voltage power MOSFETs due to its off-state voltage blocking capability, high cell-density, high current capability and its intrinsically low on-state resistance. The trench-gated MOSFET 100, as shown in the prior-art cross-section of FIG. 1A, includes an array of etched trenches lined with a thin gate oxide 104 and containing an embedded polysilicon gate 105. The entire device is formed in an epitaxial layer 102 grown atop a heavily doped substrate 101 having the same conductivity type as the epitaxial layer 102. The epitaxial layer 102, functioning as the drain of the trench gated MOSFET 100, is adjusted in thickness and dopant concentration to adjust an optimum tradeoff between off-state breakdown voltage and on-state conduction characteristics.
The MOSFET 100 is often referred to as a trench-gated DMOS device, where the “D” is an acronym for “double” originally named for the formation of the device's channel region by double diffusion (i.e., two successive diffusions one inside the other). The deeper of the two diffusions, body region 103 has a conductivity type opposite that of epitaxial layer 102, forming the body-to-drain junction of the MOSFET 100. The shallower region 106 (including regions 106A, 106B, 106C, 106D, etc.) serves as the source of the MOSFET 100 and forms a junction with the opposite conductivity type body region 103 which contains it. The MOSFET's channel region is therefore disposed vertically within body region 103 along the side of embedded gate 105.
In the illustration, the source region 106 (labeled as N+ to denote its high concentration) is N-type, body region 103 (denoted by the label PB) is P-type, while the epitaxial layer 102 (labeled as Nepi) is N-type. A MOSFET having an N-type source and drain is referred to as an N-channel device. A fabrication process for MOSFET 100 is capable of integrating from one up to millions of transistors electrically connected in parallel, but all of the N-channel variety. Alternatively the substrate, epitaxial layer, and source can be made P-type (and the body region N-type) to form an electrically parallel array of entirely P-channel devices. The net result is a device as shown schematically in FIG. 1B having only three electrical terminals: a source, a drain, and a gate, despite the integration of millions of devices. Unlike in conventional CMOS integrated circuits, there is currently no convenient way to integrate both N-channel and P-channel trench MOSFET devices into a single piece of silicon.
In sharp contrast to conventional surface MOSFETs used in ICs, the key characteristic of a DMOS device is its channel length as determined by the difference in the depth between source-body and body-drain junctions, not in the photolithographic dimensions of its polysilicon gate. Since the gate and the channel of a trench-gated MOSFET are perpendicular to the surface of the die, the current flows vertically into the bulk of the silicon, and eventually out the back of the wafer. Such a device is therefore referred to as a vertical conduction device. Thick metal 109 (typically including aluminum with some small percentage of copper and silicon) is used to facilitate contact to source region 106 and to electrically short the body region 103 to the source region 106 through shallow P+ contact regions 107 (including regions 107A, 107B, etc.) Electrical connection to the body region 103 is needed to bias the body region 103 for a stable threshold voltage and to suppress a parasitic bipolar junction transistor whose presence and significance shall be discussed in greater detail below. Electrical contact to the drain is facilitated through the backside of the substrate 101, typically by a titanium, nickel, and silver sandwich formed after wafer thinning (i.e., after fabrication has been completed).
When using diffusion processes to form the MOSFET 100, the concentration of the source region 106 is necessarily higher than the body region 103, which in turn is more heavily doped than the epitaxial layer 102. Since the body concentration exceeds that of the epitaxial layer 102, the majority of depletion spreading in the MOSFET 100 during operation under reverse bias occurs in the lightly doped epitaxial drain 102, not in the body region 103. So, the MOSFET 100 with a short channel length can support large reverse bias voltages without the risk of the depletion region “punching through” to the source region 106. Typical channel lengths are one half micron or less, even in a 30V or 100V rated device. In conventional surface MOSFETs, a half-micron channel length can only support around 5V to 10V.
In more recent inventions like those described in U.S. Pat. No. 6,413,822 (Williams, et al.), the double diffusion has been replaced with an all implanted implementation where virtually no diffusion is required. The short channel resulting from the as-implanted (i.e., dopant profiles are not redistributed by diffusion) DMOS junction is still similar to double-diffused versions except that as-implanted dopant profiles may include sequential implants of varying dose and energy and therefore need not follow the Gaussian dopant profiles characteristic of diffused junctions. Such a device may still be referred to as a DMOS, but modifying the D to symbolize the double junctions (source within body within drain), and not the double diffusion process method.
Referring again to the schematic of FIG. 1B, the equivalent circuit of the trench DMOS 120 includes an idealized MOSFET 121 and a gated diode 122. The diode 122 represents the body-to-drain PN junction formed by body region 103 and drain region 102. The gate represents the field plate effect of the polysilicon gate 105 on this junction, especially since the gate 105 overlaps into the drain region 102 with only a thin gate oxide 104 separating the two elements. While the thin gate oxide 104 is protected from rupture in its off state from depletion sharing between adjacent body regions 103, the presence of the gate 105 can adversely influence junction avalanche, both in the breakdown voltage rating of the trench DMOS 120, and in the location of the avalanche process.
This principle is illustrated in FIG. 1C where a trench MOSFET 130 is shown absent of any source region to exemplify the field plate induced breakdown concept. A reverse bias VDS applied to the junction between body 103 and epitaxial drain 102 results in carrier multiplication as shown by the contours 131 of impact ionization located in the vicinity of the trench gate 105. The ionization rates are much greater and of different shape than if the trench gates 105 were not present. The plot of gated diode breakdown BVDSS vs. gate oxide thickness Xox in FIG. 1D illustrates that oxide thickness can influence the avalanche value of the reverse biased PN junction. For the example shown, when gates-source voltage VGS is 0, i.e., when the gate 105 is tied to the p-type body, a thick gate oxide avoids oxide thickness dependence as illustrates by region 140 of the plot. For thinner oxides however, the breakdown will degrade linearly with oxide thickness as evidenced by region 141 of the plot. As labeled, the reduced avalanche value in region 141 is due to the field plate induced (FPI) breakdown effect.
Another way to illustrate field plate induced breakdown is as a plot of junction breakdown vs. gate bias as shown in FIG. 1E. In this configuration, negative gate bias, where the source is biased so as to accumulate the body majority carrier concentration, can also adversely degrade the breakdown voltage of a device. As shown, junction breakdown 142 is reduced by the presence of the field plate effect of the trench gate. Starting at some negative gate bias, typically several volts beyond the source potential (i.e., where VGS≦0), curve 143 illustrates the onset of FPI breakdown, which generally degrades BVD linearly with gate potential. Even so, the device of curve 143 exhibits minimal FPI effects since the breakdown remains at its full voltage at gate-source voltage VGS equal to 0. Curve 144 of a different device exhibits a stronger FPI effect, showing breakdown reduction even for gate-source voltage VGS equal to 0. This curve 144 represents an example where the trench gate penetrates the body by a greater extent, or with a thinner oxide than that of the device of curve 143. Clearly the adverse effects of FPI breakdown are more prevalent with thin oxide devices. Thin oxide devices, commonly employed for lower-voltage device operation in battery-powered applications, therefore exhibit higher sensitivity to FPI related problems.
One way to reduce the impact of the gate on breakdown is to electrostatically shield the bottom of the trench using deep junctions of the same conductivity type as the body regions as described in U.S. Pat. No. 5,072,266, entitled “Trench DMOS Power Transistor With Field-Shaping Body Profile And Three-Dimensional Geometry,” to Bulucea et al. FIG. 2A illustrates a portion of a trench MOSFET 150 having deep body regions 153 that are diffused deeper than the bottom of trench gates 155. Deep body regions 153 have the same potential as body regions 156, but typically have a higher dopant concentration. Both regions 153 and 156 are contacted at the surface by heavily doped contact regions 157.
The electrical properties of trench MOSFET 150 can be represented by the schematic shown in FIG. 2B where MOSFET 171 includes a gated diode 172. But rather than the gate of the gated diode 172 being connected directly to the gate of the MOSFET 171 as in the flat bottom body device 120 of FIG. 1B, the device 150 of FIG. 2A exhibits an effect best explained as that of a JFET 173 connection between the actual gate of the device 150 and the gate describing the FPI gated diode effect. At sufficient reverse bias, the depletion regions spreading from the adjacent deep body regions 153 merge together and essentially pinch off or disconnect the field plate effect from the junction potential (see cross-hatched region of FIG. 2C). The FPI effect is then greatly diminished in magnitude, and a high breakdown is preserved.
FIG. 2B also illustrates the addition of a zener diode 174 representing the PIN junction formed between deep body region 153 and heavily-doped substrate 151. In a high current avalanche, most of the current flows through the heavily doped region body region 153 rather than through body region 156 as illustrated in FIG. 2D. The deep region 153 forms a junction that carries more current in avalanche due to its lower breakdown voltage (as illustrated by the ionization contours) and lower series resistance (being more highly doped than the body region 156). The breakdown of zener diode 174 is lower than gated diode 172 since the region 153, which forms the diode's anode, is in closer proximity to substrate 151 than that of shallow body 156, thereby reducing its PIN breakdown voltage. So since this breakdown occurs at a lower voltage than the body junction breakdown, deep body region 153 adds a second degree of protection by clamping the maximum drain voltage to a lower value and never letting the voltage rise to the point that field plate induced breakdown occurs. Avoiding FPI breakdown is advantageous since the FPI breakdown involves semiconductor surfaces and interfaces that may charge and therefore are intrinsically less reliable than bulk silicon avalanche breakdown. It should be noted the term “zener” is not in reference to a zener breakdown mechanism (a type of tunneling phenomena), but simply refers to the voltage clamping action of the diode.
Whilst the deep body region 153 can greatly improve the robust character of the trench MOSFET 150 in avalanche, the deep body region 153 also imposes some problematic limitations in the on-state performance of the trench MOSFET 150. FIG. 2E, for example, illustrates that current in the on-state condition flows vertically from the topside sources 158 along the gate oxide 154 within the body regions 156A then expands or spreads into the epitaxial layer 152 after passing the bottom of the trench.
The spreading of current indicates that the entire cross-sectional area is not being fully utilized in carrying current. Hence, the device is not operating at its theoretical lowest on-state resistance. Moreover the spreading angle of the current (which unimpeded occurs at approximately 45°) becomes further limited by the intrusion of the lateral diffusion of the deep body regions 153. In fact, epitaxial layer portions 177A and 177B directly beneath deep body regions 153 never carry any current at all, contributing to a higher resistance.
The on-resistance penalty of deep body diodes surrounding each trench gate 155 becomes even more problematic as cell dimensions are decreased (i.e., at higher cell densities). In FIG. 2F, for example, an increase in cell density ideally should increase the number of parallel transistors, thereby reducing the overall resistance of a given area device. To avoid comparing devices of dissimilar area, the on-resistance RDS is often normalized by the area A and described by a figure of merit known as specific on-resistance RDSA, having units of on-resistance times area such as mΩcm2. In region I (for densities below approximately 12 Mcell/in2), an increase in cell density reduces specific on-resistance as expected. Above that density, in region II, the limitation of the deep body on confining the current spreading in the epitaxial layer causes an increase in on-resistance per cell that offsets the benefit gained by having more parallel conducting cells in the same region. The limitation of current spreading results in a constant specific on-resistance, so that no benefit in resistance is gained by increasing the cell density. In region III (for densities above for example 24 Mcells/in2), the on-resistance starts to climb rapidly. This effect occurs when the high concentration of the deep body begins to adversely interfere with the channel concentrations thereby increasing the threshold voltage of the device.
FIG. 2G illustrates a top view of a closed cell array (in this case square) of a trench-gated MOSFET 180 illustrating the polysilicon filled trench regions 181, and mesa regions 182 between the trenches, along with the deep body regions 183 located within each mesa region 182. Whenever the spacing between deep body regions 183 and the trench regions 181 gets too close, the high concentration of the deep body regions 183 adversely interfere with the channel concentrations as noted above. This effect can result from making the deep body regions 183 too large, or by shrinking the cell pitch without shrinking the deep body region by a proportional amount. The deep body regions 183 must have at least a minimum size to be diffused past the bottom of the trench. If the deep body region 183 becomes smaller than its depth, the diffusion will start to exhibit starved diffusion effects (where the surface concentration along the entire surface is affected by both lateral and vertical diffusion). The effect of starved diffusion is that the junction depth of the deep body will become shallower than in wider areas and will not reach below the bottom of the trench, hence no benefit will be gained from the presence of the deep body.
In an alternative approach described in U.S. Pat. No. 6,140,678, entitled “Trench-Gated Power MOSFET with Protective Diode” to W. Grabowski, R. Williams, and M. Darwish, the deep body region is not introduced into every mesa region, but instead is limited to a fraction of the device's mesa regions, typically 1/16th of the total active device cells. In FIG. 3A, the cross-section of device 200 illustrates an array of trenches with gate oxide 204 and embedded trench polysilicon 205 formed in an epitaxial layer 202 atop a heavily doped substrate 201. The body diffusion (collectively as 203) is formed in every mesa region between the trenches including active channel portions 203A, 203B, 203C, 203E, and 203F. Body region 203D is formed in a diode-only cell lacking a source but integrating a deep body region 209 (labeled as dP+ in the N-channel example as shown) having a width ydP+, which may extend entirely between two adjacent trenches.
While the device 200 looks like the device 150 of FIG. 2A, operation of device 200 is substantially different and phenomenologically indicated in schematic FIG. 3B. In FIG. 3B, the MOSFET 220 and zener diode 222, which is in parallel with MOSFET 220, have dissimilar areas. Their respective areas, as denoted by the label “1/A” for the diode and “(n−1)/A” for the MOSFET, describe that in an active area A (comprising n cells) 1 cell will constitute a diode cell and the other (n−1) cells include active transistors. The active transistors also contain their integral body-to-drain PN junction diode 221, gated by the trench gate electrode. The benefit of deep-body charge sharing (the JFET effect) that minimizes gated diode breakdown in the device 150 of FIG. 2A is lost in the 1-of-n design since the deep body is not present in or near every cell. Without the charge sharing effect, the protection of the device falls totally on the zener diode, which is repeated at a regular interval, sparsely yet uniformly. Note that without charge sharing, the zener breakdown voltage of diode 222 must therefore have a breakdown lower than that of gated diode 221 to provide any degree of protection.
In an “n” cell device, 1-of-n cells include the protective zener diode clamp 222, and the rest of the cells include active devices. The layout is best understood by a top view of a closed cell array vertical trench gated MOSFET shown in FIG. 3C. In such a design, the trench gate array 231 contains a repeated array of sixteen cells, fifteen cells containing active devices 234 and one diode cell 232 containing a deep body 233. The entire array repeats at regular intervals.
In principle, the diode clamp 222 formed by deep body opening 233 limits the maximum voltage imposed upon the device. The contact and junction area of the zener diode must be of adequate area to carry the avalanche current without damage. Practically speaking, however, the deep body dimension ydP+ must generally be smaller than the mesa region 232 or the lateral diffusion of the deep junction will spill over into adjacent active cells and prevent their conduction.
FIG. 3D illustrates the 1-of-n design operating in avalanche, carrying current while sustaining a high voltage and high fields at the point of silicon avalanche. In proper operation, deep body 209 sustains the highest fields in the device, and the ionization contours indicate the breakdown and resulting current flow occurs at the bottom of the deep body diffusion far away from trench gate oxide 204. To keep the ionization low in the vicinity of the trench gate (under body 203C near the trench), the avalanche breakdown of deep body diode 209 to epitaxial layer 202 must be substantially lower than the breakdown of body 203C to epitaxial layer 202 junction gated by the trench gate.
This principle is illustrated in the graph of FIG. 3E where the component diode breakdown voltages BV are shown as a function of the gate oxide thickness Xox. The breakdown BV(PB) of the flat body junction has an avalanche voltage given by line 242 until the gate oxide gets thin enough to induce field plate induced breakdown shown by line 243. The avalanche breakdown voltage BVZ of deep body zener diode clamp given by line 240 is intentionally designed to be lower than that of the body diode (line 242) so that breakdown will not occur near the trench gate. A voltage margin of 4V to 10V is desirable to allow for manufacturing variations so that the FPI breakdown voltage never falls below the zener voltage.
Whenever the FPI breakdown drops below the zener voltage BVz of line 240, the device is no longer protected. This problem occurs for higher epitaxial dopant concentrations in the epitaxial layer and for thinner gate oxides, conditions needed to optimize low voltage trench devices for the lowest possible on-resistances. This effect is further exemplified in the graph of FIG. 3F illustrating the epitaxial concentration dependence of the PN junction transitioning from avalanche breakdown 250 to FPI breakdown 251 at higher epitaxial concentrations. The zener voltage BVz shows very little concentration dependence in region 253, while the zener diode is in PIN reach-through avalanche, i.e., when its depletion region at avalanche has completely depleted the epitaxial layer (or more specifically the net epitaxial layer between the bottom of the deep body junction and the top of the heavily doped substrate). At a higher dopant concentration, the epitaxial layer no longer depletes, and the diode shows the classic PN doping dependence of region 254. Before that happens, however, the FPI breakdown of the body junction drops below BVz and the device is no longer protected.
In conclusion, the 1-of-n clamp is limited in its ability to clamp and protect against FPI breakdown in low voltage devices. For example, to protect a 30V rated MOSFET with a thin gate oxide, the zener must be designed to breakdown at 34V, and the gated body diode must use light enough epitaxial doping to breakdown above 40V. In essence a 40V MOSFET is used to operate safely at 30V. The extra 10V avalanche guard-band means the device has the on-resistance of a 40V device not a 30V device. This method still results in a higher than desirable on-resistance, albeit not as severe as in device 150 of FIG. 2A.
A method to reduce the impact of the FPI breakdown problem is described in U.S. Pat. No. 6,291,298 to Williams et al., which is incorporated herein in its entirety. As shown in FIG. 4A a trench gated vertical power MOSFET 300 shown in cross-section having trench gates with embedded polysilicon gates 304A to 304C (collectively referred to as gates 304) and thin sidewall gate oxides 310A to 310C (collectively referred to as sidewall gate oxide 310), incorporates a region of thick oxide 303A to 303C (collectively referred to as thick bottom oxide 303) located at the bottom of each trench. The thick bottom oxide (TBOX) with a typical thickness of 2 kÅ greatly reduces the influence of the trench gate on the junctions formed by body regions 305A to 305D (collectively referred to as body 305), reducing field plate induced impact ionization, protecting against oxide wear-out from carrier injection at the trench bottom, and reducing drain-to-gate overlap capacitance. The effect of the thickness of sidewall gate oxide 310 on the PN junction breakdown of body 305 to epitaxial layer 302 is greatly diminished in the presence of the TBOX region 303, especially if the body of gate polysilicon 304 only overlaps just beyond body 305. The body regions are shown to be more optimally formed using high energy ion implantation and as-implanted dopant profiles not redistributed by thermal diffusion.
The device is shown with uniform cells having source regions 306A to 306D shorted to metal 311 and also contains contacts to the body regions 305, contacted by metal 311 in the 3D projection of the device (not shown in the particular cross-section of FIG. 4A). Each trench is insulated from the source metal by a top dielectric 308A to 308C. The equivalent schematic of the device 300 is shown in FIG. 4B containing a MOSFET 320 in parallel with body-to-drain junction 321. No zener diode clamp is present, nor is any substantial field plate induced breakdown mechanism present.
FIG. 4C illustrates the advantage of the thick bottom oxide in surviving avalanche without the need for voltage clamping. Biasing the trench device into avalanche (shown in simplified form as a gated diode in FIG. 4C), the ionization contours illustrate avalanche occurring at the trench bottom against TBOX region 303B and not near the overlap of thin gate oxide 310B beyond body region 305C. In this structure, minimal hot carriers are injected into thin sidewall gate oxide 310B, despite the proximity of gate electrode 304B to the junction formed by body regions 305B, 305C and the opposite conductivity type epitaxial layer 302. The hot carrier reliability of such a device is greatly improved over an unclamped device with an entirely thin gate oxide lining the trench. Furthermore, the breakdown of such a device shows minimal dependence on the thickness of gate oxide 304B. Note however that some lateral current flow during avalanche may occur within body region 305 (as shown in the body region 305C of FIG. 4C). This lateral current flow is undesirable when compared to purely vertical current flow, a matter of important consideration discussed below.
FIG. 5A illustrates the phenomena of hot carrier trapping and oxide wear-out in a conventional uniform gate oxide trench-gated diode 340 (or any similar trench gated MOSFET). The presence of gate electrode 346 induces FPI carrier generation of a reverse bias junction between body 343A, 343B and epitaxial layer 342. Including curvature effects of the trench that locally enhance the electric fields in region 350, electron-pairs are generated via impact ionization. Even at a voltage below avalanche, these carriers are accelerated by the high localized electric fields of the reverse biased junction, the electrons being swept toward the wafer's backside contact and the holes being accelerated toward the negatively biased gate electrode. If the holes gain sufficient energy, they can overcome the energy barrier of the oxide-silicon interface and bury themselves into the oxide 345, gradually charging and damaging the thin gate oxide 345.
In contrast, a trench gated device 360 having a TBOX region 361 as illustrated in FIG. 5B exhibits impact ionization induced hot carrier generation primarily in a region 367, which leads to hot-hole injection into thick oxide 361 with virtually no effect on device reliability. Only hot carrier generation in a region 368 in the vicinity of thin sidewall gate ox 362 can degrade the conduction characteristics and long term reliability of device 360. Since the failure mode is a stochastic process and statistical phenomena, the small cross-sectional area of region 368 leads to minimal charge injection and in the worst case causes very slow degradation. With such low injection, twenty years or more of reliable operation and product lifetime are achievable. So while thick bottom oxide 361 avoids hot carrier induced damage, thick bottom oxide 361 does not protect fully against double injection effects, which may occur during high current avalanche conditions.
This double injection effect is illustrated in FIG. 6A, where the a thin gate trench gated vertical power MOSFET 380 not only includes the gated diode structure of the prior illustration (including gate 385, thin gate oxide 384, body regions 383A, 383B and highly doped body-contact regions 386A, 386B) but also includes opposite conductivity type source regions 387A, 387B (shown as N+ regions). The pre-avalanche current from impact ionization as shown by the current flow lines includes electrons in the n-type epitaxial layer 382 and holes in the p-type body region flowing laterally within body region 383B into body contact P+ region 383B. Assuming the body 383B remains relatively undepleted during such operation, the hole current in the P-type body region 383B constitutes majority carrier conduction. As shown in FIG. 6B, hole conduction in p-type material exhibits a voltage drop associated with the parasitic resistance rb and an increase in the potential of the body region 383C to a voltage VB(y) above the source/body ground potential (zero volts). So, the gated diode 391 creates a FPI ionization current that results in a de-biasing of the body voltage. If voltage VB(y) exceeds the potential of N+ source 387C by more than 0.6V (i.e., a forward biased diode voltage), then N+ source 387C will begin to inject electrons into the thin p-type body region 383C. These injected electrons give rise to a collector current of a parasitic NPN bipolar including N+ source 387C as emitter, P-type body 383C as base, and N-type epitaxial layer 382 as collector, hence the name double injection. This electron current flow is electrically in parallel with the gated diode current leading to positive feedback and a potential runaway condition, especially at high temperatures. The positive feedback of the NPN parasitic worsens at high temperatures, leading to localized heating, hot spots, and device burnout from high local current densities.
The solution to the double-injection problem is to keep the length of N+ region source region 387C short so that the resistance rb remains low, and to keep the concentration of the body region 383C as high as possible (given a target threshold voltage and gate oxide thickness). This principle of a good source-body short is clearly illustrated schematically in FIG. 6C where MOSFET 400 includes drain-to-body PN diode 401 (which may include FPI effects in avalanche) along with parasitic NPN transistor 403, and a source-body shorting contact that still has some parasitic base resistance 402 of magnitude rb. If the short is perfect and ideal, resistance rb will remain zero and the NPN transistor 403 can never turn on, avoiding electron injection from the N+ source and hence avoiding the risk of sustaining voltage snapback as illustrated in the current ID vs. drain-source voltage VDS characteristic shown in FIG. 5D.
The resistance rb remains difficult to minimize especially in narrow mesa trench gated power MOSFETs that lack adequate room to contact the P+ body contact along the entire length of the body region. In a device 500 having cross-sections shown in FIG. 6E and FIG. 6F, the resistance rb to the P+ contact 505A can be substantial, especially for current flowing within P-type body 503 under N+ source 504A. The source must be interrupted to make room to contact the P+ contact 505A leading to an undesirable tradeoff between the amount of source perimeter (lower on-resistance) and the body contact P+ (reduced resistance rb and improved snapback).
So in summary, double injection can lead to a further reduction in the off-state blocking characteristics of a trench-gated power MOSFET to voltages below that resulting from field plate induced (FPI) impact ionization and FPI avalanche current. Moreover, without a voltage clamp, it is difficult to shunt (i.e., reroute) high avalanche currents away from the trench edge (to avoid lateral current flow in the body region) and to thereby suppress double injection induced snapback. The deep-body method such as implemented in device 150 of FIG. 2A and the distributed (1-of-n type) diode clamp such as implemented in device 200 of FIG. 3A suppress double injection but increase device on-resistance. The added resistance is a severe limitation to cell density for device 150, which requires a deep body in every cell. The resistance increase in the distributed clamp is also substantial, needing at least 10V of overdesign to avoid FPI breakdown (which can lead to 20 to 40% increases in on-resistance) while still not completely eliminating FPI impact ionization currents.
As shown in the cross-section of device 550 in FIG. 7, using the 1-of-n clamp concept but with a shallow heavily-doped body 554 or shallow-zener voltage clamp does not adequately protect the device 550, since the trench gate 556A, 556B is deeper than the clamping diode junction, and therefore breaks down first. As an example, asymmetries in the device manufacturing can even cause the avalanche to occur on one side of the trenches, e.g., in regions 558 and 559, rather than uniformly on both sides, making double injection more likely due to the localized high ionization currents.
The thick bottom oxide has been shown to reduce FPI impact ionization currents, increase the onset of avalanche, and raise the device's breakdown voltage, but by itself cannot guarantee that the onset of double injection can be prevented, especially when and if the device is driven into high current breakdown operation (a condition common for power application circuits with inductive loads).
Available methods to clamp the voltage (and divert avalanche currents) to avoid snapback in trench gate power MOSFETs lead to increased on-resistance, and available methods to reduce impact ionization from thin-gate field-plate-induced (FPI) effects do little to prevent double injection and snapback. What is needed is a device that avoids (or at least minimizes) FPI impact ionization (even for thin gate oxides) while still clamping or diverting avalanche current without undue increases in on-state reduction.